Internet-based Radar Digital Receiver and Processor (iRAP)

The RSS Internet-based Radar Digital Receiver and Processor (iRAP) system provides a novel, high fidelity, modular processing system for radar applications. Easily reconfigurable at both hardware and firmware levels, it provides a cost effective solution that can be optimized for each application. Some of its many highlights are:

  • Compact, Conduction Cooled 3U solution.
  • Linux-based network processor module (NPM) provides 4 independent GigE interfaces.
  • PCIe (x8 root complex) and PCI switch fabricate supporting up to 48 ports.
  • Local point-to-point data bus providing up to 25.6 Gb/s inter-card data rates.
  • Parallel processing with up to 4/8 FPGA Processing Modules (FPM) per system (Virtex SX95T).
  • High fidelity FPGA firmware such as a multi-channel match filter digital receiver supporting up to 16 independent sub channels and 400 MHz, 100 percent duty cycle.
  • Standard and custom designed mezzanine cards the plug into FPM allowing it to take on many personalities (e.g. digital receiver, AWG, etc.).
  • Novel FPGA-based DMA engine providing 5 Gb/s data transfer to NPM.
  • Proven technology – deployed on NASA Global Hawk UAV and ER-2 aircraft operating at altitudes up to 70 kft unpressurized.

Partners and Related Technologies and Missions:

Contact RSS for more information.

HIWRAP installed on NASA Global Hawk UAV

View Image
Network Processor
The network processor module (NPM) is the iRAP configuration and data management server, which enables iRAP, and those sensors/radars connected to it, to seamlessly integrate into network environments. With four independent GigE network interfaces, its Linux-based processor can communicate with client applications, processors, data storage devices and other systems over the local and remote networks. Using a XML-based object oriented configuration API, the NPM provides a powerful but simple means to configure and monitor all iRAP modules, and its embedded data processor / router distributes iRAP data and products at rates as high as 120 MB/s per network interface.
Features
  • PowerQUICC Processor
  • Open Source Operating System
  • PCI Express and SerDes Support
  • Redundancy for High Availability Solutions
  • Ultra Fast Network Data Communications
  • Proven High Altitude Operations
  • 3U Conduction Cooled Design
Specifications
  • MPC8548E Processor
  • 2 GB RAM
  • Linux 2.6 Kernel
  • Four 1 GB Ethernet Network Interfaces
  • x8 PCIe Root Complex
  • Dual RS-232 Ports
  • Multiple Simultaneous DMAs
  • Operating Temperature Range: -40°C to +80°C
  • Operating Altitudes up to 70 kft Unpressurized
Mechanical
  • Standard 3U CompactPCI Form Factor
  • Conductive Cooled
  • Heat Plate with Wedge Locks
View Image
Switch Fabric
The Switch Fabric Module (SFM) implements the system interconnect switch optimized for PCIe packet switching supporting multiple simultaneous peer-peer traffic flows. This switch connects the iRAP Network and FPGA processor modules through the backplane enabling very high bandwidth data communications between these modules.
Features
  • High Performance PCIe Switch
  • Flexible Architecture with Automatic Negotiations
  • On-chip Packet Buffering
  • RAS Features
Specifications
  • Supports up to 12 ports and 48 lanes (2.5 Gbps SerDES per lane)
  • 192 Gbps aggregated switching capacity
  • Supports payloads up to 2048 bytes
  • Automatic port link negotiations to x8, x4, x2 or x1
  • Automatic lane reversal and polarity inversion
  • Redundant upstream port failover capability
  • PCIe end-to-end CRC checking
  • PCIe Base Specification Revision 1.1 compliant
  • Operating Temperature Range: -40°C to +80°C
  • Operating Altitudes up to 70 kft Unpressurized
Mechanical
  • Standard 3U CompactPCI Form Factor
  • Conductive Cooled
  • Heat Plate with Wedge Locks
View Image
FPGA Module
The iRAP FPGA Processor Module (FPM) is a novel high-fidelity FPGA-based processor. Within its Xilinx FPGA, radar processing algorithms, such as multi-channel complex IF demodulation and filtering, pulse compression, arbitrary waveform generation, spectral processing and much more, can be executed in real-time. With interchangeable mezzanine cards, the same card can assume different responsibilities while maintaining the same interface and firmware for communicating over the PCIe and local processing buses.
Features
  • Xilinx FPGA processor
  • On board high bandwidth memory
  • Parallel buses for simultaneous, high bandwidth inter-card communications
  • High bandwidth LVDS mezzanine bus enabling daughter card expansion
  • On board and external clock interfaces
  • High performance firmware options for radar applications
  • Custom algorithm development / firmware services
Specifications
  • Virtex SX95T FPGA.
  • 400 MHz, 37 bit wide QDR SRAM (72 & 144 Mbit)
  • High bandwidth system bus (x2 PCIe)
  • Local processing bus with point-to-point communication (x2 SerDes) to each processing slot
  • LVDS mezzanine bus providing two x16 data buses with separate clocks and configuration bus
  • High speed LVDS digital I/O interface (x8)
  • 50 ohm external clock interface
  • Firmware including multi-channel (up to 16 sub channels) complex digital receiver supporting up to 400 MHz bandwidth, video filtering and pulse compression
  • Embedded x2 PCIe DMA engine
  • Operating Temperature Range: -40°C to +80°C
  • Operating Altitudes up to 70 kft Unpressurized
Mechanical
  • Standard 3U CompactPCI Form Factor
  • Conductive Cooled
  • Heat Plate with Wedge Locks
View Image
Mezzanine Cards
Mezzanine cards offer the next level of configurability to the FPGA processor module (FPM) by providing it at the hardware layer. This offers a cost effective modular means to expand the capabilities of the FPGA processor module (FPM), and at the same time offers a very high bandwidth standardized communication bus between the FPGA and these modules. Current mezzanine cards include a dual 14-bit, 400 MSa/s ADC and a quad channel fiber communications mezzanine card. They are deployed with the FPM in a single slot. Custom mezzanine cards can be designed and fabricated at the fraction of the cost of building a new FPM.
Features
  • Modular hardware expansion
  • Ultra high bandwidth, multi lane data communication with FPM FPGA
  • Compact design maintaining single 3U-slot deployment with FPM
  • Enables phased development
Specifications
  • Two x16 lane LVDS data buses to FPGA
  • Two x4 lane LVDS bus to FPGA for high speed clock and control signals
  • LVDS lanes matched (< 50 ps)
  • 20 single-ended data lines to FPGA for lower bandwidth, control and status signals
  • Standardize API and FPGA firmware for data communication
  • Dual 14-bit, 400 MSa/s ADC mezzanine card
  • Quad 2.5 SerDes Channel Fiber mezzanine card
  • Operating Temperature Range: -40°C to +80°C
  • Operating Altitudes up to 70 kft Unpressurized
Mechanical
  • 3U width, ½ length daughter card
  • Conductive Cooled
  • FPM Heat Plate Accepts Mezzanine Card
View Image
External Modules
The iRAP external modules further extend the capabilities and flexibility of iRAP system. Designed to operate standalone or with the iRAP system, these modules can be deployed remote to the iRAP system. External modules include ultra high bandwidth analog-to-digital (ADC) sampler, arbitrary waveform generator (AWG), and radar control & timing unit (CTU). High speed, multi-channel fiber mezzanine card that plugs into the FPGA processing module (FPM) can be deployed to communicate with these modules when very high-speed communications to the iRAP system are required.
Features
  • Modular and embedded hardware expansion
  • Remote and standalone operations
  • Compact, conductive cooled designs
  • Current modules include 12-bit, 3.6 GSa/s ADC module with dual channel fiber communications channel and) AWG & radar timing and control module with daughter card
Specifications
3.6 GSa/s ADC external module:
  • 3.6 GSa/s, 12-bit sampling with 1.75 GHz full power bandwidth
  • IF input signal (30 MHz – 1.75 GHz, 0.707 Vpp, 50 ohms)
  • 9.4 ENOB, -153.5 dBm/Hz full bandwidth noise power density
  • -61 dBFS IMD3
  • Option: 2 IF channels at 1.8 GSa/s
  • External sampling clock (1.8 GHz, 0 dBm, 50 ohms) input
  • External timing synchronization clock (10 MHz, LVDS) input
  • LVDS synchronization signal (input/output) for multiple device synchronization
  • Xilinx SX50T FPGA
  • Dual fiber (SerDES) communications providing 5 Gbps data communication
  • Real-time clock (48-bits, 100 nsec resolution) with LVDS PPS
AWG / Radar TCU
  • Fixed frequency and frequency modulated (linear and nonlinear) waveforms (0 dBm max, 50 ohms output signal)
  • Amplitude tapering (14 bits, 250 MHz)
  • Internal or external 1 GHz AWG clock (0 dBm, 50 ohms)
  • 10 MHz input clock for timing and control (0 dBm, 50 ohms)
  • Xilinx Spartan 6 FPGA
  • Eight RJ-45 interfaces for LVDS input/output timing and control signals
  • Mezzanine bus for customized daughter card: Standard daughter card has 48-pin miniature D-Sub for radar timing & control, RS-232 interface and Xilinx CPLD (XCR3256XL)
  • Standalone or Internet-based GUI for configuration and control
  • Microblaze controller
  • Operating temperature: -40°C to +80°C
  • Operating altitude up to 70 kft unpressurized
Mechanical
  • Conduction cooled enclosures with vertical and horizontal mounting tabs